METHOD FOR REDUCED POWER CLOCK FREQUENCY MONITORING

摘要

An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

主权项

1. An apparatus, comprising:
a first clock monitoring circuit configured to:
receive a first clock signal;assert a first signal in response to a determination that the frequency of the first clock signal is greater than a first upper threshold value; andassert a second signal in response to a determination that the frequency of the first clock signal is less than a first lower threshold value; and a second clock monitoring circuit configured to:
receive a second clock signal, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal;compare, dependent upon the first clock signal, the frequency of the second clock signal to a second upper threshold value and a second lower threshold value;assert a third signal if the frequency of the second clock signal is greater than the second upper threshold value; andassert a fourth signal if the frequency of the second clock signal is less than the second lower threshold value; wherein a power consumption of the second clock monitoring circuit is less than a power consumption of the first clock monitoring circuit.