发明名称 Method and apparatus for reducing row shut-off time in an interleaved-row memory device
摘要 A semiconductor memory includes two pull-down transistors provided at opposite ends of each word line of an interleaved-row array memory. Both of these transistors receive the same global phase signal and are therefore both rendered conductive when a word line is deselected. The two pull-down transistors, acting together, sink sufficient current to rapidly pull down each word line of an interleaved-row array DRAMs, thus minimizing shut-off time.
申请公布号 US5986946(A) 申请公布日期 1999.11.16
申请号 US19960692950 申请日期 1996.08.07
申请人 MICRON TECHNOLOGY, INC. 发明人 SHIRLEY, BRIAN
分类号 G11C8/08;G11C8/14;(IPC1-7):G11C8/00 主分类号 G11C8/08
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