SAMPLING CLOCK GENERATING CIRCUIT WHICH GUARANTEES INPUT SET-UP/HOLD TIME MARGIN, METHOD THEREOF, SYNCHRONIZED SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM WHICH INCLUDES THE SAME SAMPLING CLOCK GENERATING CIRCUIT

摘要

A sampling clock generating circuit capable of guaranteeing input set-up/hold time margin, a method thereof, a synchronous semiconductor memory device and a memory system are provided to operate the memory system smoothly in a high speed operation by guaranteeing the input set-up/hold time margin of a command and an address inputted to the semiconductor memory device. A clock input buffer(110) generates a first internal clock signal by buffering an external clock signal applied from the outside. A level sensing pulse generation part(120) receives the first internal clock signal, and generates unit sensing pulses with a fixed duration in response to each rising edge of the first internal clock signal. A logic level latch part(130) receives the unit sensing pulses and a chip selection signal, and latches the logic level of the inputted chip selection signal by using the unit sensing pulses, and outputs the latched logic level as a signal. A sampling clock generation part(140) receives the logic level signal, an MRS_NT control signal and the first internal clock signal, and generates a second internal clock signal by masking the first internal clock signal at every N period according to the MRS_NT control signal, when the logic level signal becomes a logic low state.