LEVEL SHIFTER CIRCUIT

摘要

A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal. The first control bias unit includes a third transistor and a fourth transistor coupled to the first transistor and second transistor respectively and their gates are controlled by a first bias. The output stage includes a fifth transistor and a sixth transistor coupled to the third transistor and fourth transistor respectively and their gates are coupled to the first output terminal and second output terminal. The second control bias unit includes a seventh transistor and an eighth transistor coupled to the fifth transistor and sixth transistor respectively and their gates are controlled by a second bias.

主权项

1. A level shifter circuit applied in a driving circuit of a display and converting an input signal having a first voltage into an output signal having a second voltage, the level shifter circuit comprising:
an input terminal configured to receive the input signal; a first output terminal and a second output terminal configured to output the output signal respectively; an input stage comprising a first transistor and a second transistor, wherein gates of the first transistor and the second transistor are coupled to the input terminal; a first control basis unit comprising a third transistor and a fourth transistor coupled to the first transistor and the second transistor respectively, wherein gates of the third transistor and the fourth transistor are controlled by a first bias; an output stage comprising a fifth transistor and a sixth transistor coupled to the third transistor and the fourth transistor respectively, wherein gates of the fifth transistor and the sixth transistor are coupled to the first output terminal and the second output terminal respectively; and a second control bias unit comprising a seventh transistor and an eighth transistor coupled to the fifth transistor and the sixth transistor respectively, wherein gates of the seventh transistor and the eighth transistor are controlled by a second bias; wherein the first transistor, the second transistor, the third transistor and the fourth transistor are N-type transistors and the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors.