发明名称 |
INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME |
摘要 |
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via. |
申请公布号 |
US2016358851(A1) |
申请公布日期 |
2016.12.08 |
申请号 |
US201514729188 |
申请日期 |
2015.06.03 |
申请人 |
GLOBALFOUNDRIES, INC. |
发明人 |
Singh Sunil Kumar;Srivastava Ravi Prakash;Wu Xusheng;Sehgal Akshey;Tang Teck Jung |
分类号 |
H01L23/522;H01L21/02;H01L23/532;H01L21/768 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
1. A method for fabricating an integrated circuit, the method comprising:
depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer; forming a patterned hard mask overlying the OILD layer to form a first target metal line trench pattern and a second target metal line trench pattern; forming a patterned mask overlying the hard mask and the second target metal line trench pattern to form a target via-hole pattern in the first target metal line trench pattern; forming a via-hole extending through the target via-hole pattern and in the OILD layer; removing the patterned mask overlying the second target metal line trench pattern; forming a metal line trench extending through the second target metal line trench pattern and in the OILD layer; depositing a conductive metal fill in the via-hole for forming a via and in the metal line trench for forming a metal line; and planarizing the conductive metal fill to expose an upper surface portion of the OILD layer. |
地址 |
Grand Cayman KY |