CLOCK DELAY ANALYSIS DEVICE, CLOCK DELAY ANALYSIS METHOD, CLOCK DELAY ANALYSIS PROGRAM AND RECORDING MEDIUM

摘要

PROBLEM TO BE SOLVED: To lighten up the pessimism of a design margin by accurately estimating the stable minimum clock delay value (slack) of an object circuit. SOLUTION: When circuit information 410 is inputted to an input part 401, a clock delay analysis device 400 extracts the delay distribution information of a circuit element configuring a data path DP and a clock path CP from a circuit element delay distribution information database 300 by an extracting part 402. The delay distribution information(mean value mda and standard deviationσda) of the data path DP is calculated by the statistical superimposition of a data path delay distribution information calculating part 403, and the delay distribution information (mean value mck and standard deviationσck) of the clock path CP is calculated by the statistical superimposition of a clock path delay distribution information calculating part 404. A delay difference distribution information (mane value m and standard deviationσ) between the data path DP and the clock path CP is calculated by a delay difference distribution information calculating part 405. COPYRIGHT: (C)2007,JPO&INPIT