| 摘要 |
PROBLEM TO BE SOLVED: To avoid both errors of setup error generated by increase of a delay time due to random fluctuation in a path for determining operation frequency and holding error generated by reduction in the delay time due to random fluctuation, in a path having severe holding restriction of a flip-flop, because fluctuation in process generated at random among MOSFETs becomes distinctive. SOLUTION: A semiconductor integrated circuit is provided with flip-flop circuits FFa, FFb, and FFc, a combined circuit 5 connected to the flip-flop circuits, clock buffers CBa, CBb, and CBc for supplying a clock to the flip-flop circuits, and control circuits 2, 3 for independently controlling a delay time of the flip-flop circuits and combining circuit 5. The holding error can be suppressed by providing a longer delay time for the flip-flop circuit, and the setup error is suppressed by shortening the delay time for the combined circuit. COPYRIGHT: (C)2008,JPO&INPIT
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