| 摘要 |
ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, the ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operable to generate the updated state metric for the state at the current trellis stage as well. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.
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