| 发明名称 |
Zero-Misalignment Via-Pad Structures |
| 摘要 |
A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer. |
| 申请公布号 |
US2016183370(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201414576107 |
申请日期 |
2014.12.18 |
| 申请人 |
Intel Corporation |
发明人 |
Rawlings Brandon M.;BRAUNISCH Henning |
| 分类号 |
H05K1/11;H05K1/09;H05K3/06;H05K3/40;H05K3/02;H05K1/02;H05K3/46 |
主分类号 |
H05K1/11 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method to manufacture an electronic device, comprising:
depositing a photoresist on a seed layer on a substrate; removing a first region of the photoresist to expose a first portion of the seed layer to form a via-pad structure; depositing a first conductive layer onto the first portion; removing a second region of the photoresist adjacent to the first region to expose a second portion of the seed layer to form a line; and depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer. |
| 地址 |
Santa Clara CA US |
