ＳＧＴを有する半導体装置とその製造方法

摘要

A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power supply wiring metal layer and the P+ region and between a ground wiring metal layer and the N+ region are established on the entire surfaces of low-resistance Ni silicide layers that are respectively in contact with the P+ region and the N+ region and formed on outer peripheries of the Si pillars. Lower ends of the power supply wiring metal layer and the ground wiring metal layer are located at a height of surfaces of HfO layers near the boundaries between the P+ region and a channel and between the N+ region and a channel, respectively.