| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve throughput by reducing a hardware latency when software processing is generated in the last half of a job. Ž<P>SOLUTION: A data processor configured of a logic circuit and a processor for processing a plurality of tasks while synchronizing the logic circuit with the processor is provided with: a buffer means for buffering a plurality of tasks which are executed by the logic circuit or the processor; a task scheduler for scheduling the buffered tasks; and a storage means for storing the scheduled tasks. The logic circuit performs multi-thread processing by switching the scheduled tasks. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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