Vertical thin film transistor selection devices and methods of fabrication

摘要

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.

主权项

1. A method of forming a vertical thin film transistor (TFT) select device, comprising:
forming a first vertical TFT select device including a body, a first source/drain (S/D) region and a second S/D region over a substrate, the first S/D region coupled to a first vertical bit line, the second S/D region coupled to a global bit line; forming a second vertical TFT select device including a body, a first source/drain (S/D) region and a second S/D region over a substrate, the first S/D region coupled to a second vertical bit line, the second S/D region coupled to the global bit line; forming a gate dielectric after forming the body, the first S/D region, and the second S/D region of the first vertical TFT select device and the second vertical TFT select device; etching to form a first gate for the first vertical TFT select device and a second gate for the second vertical TFT select device after forming the gate dielectric, the first gate is separated from the body of the first vertical TFT select device by the gate dielectric and has a lower surface that is separated from the global bit line at least partially by a void, the second gate is separated from the body of the second vertical TFT select device by the gate dielectric and has a lower surface that is separated from the global bit line at least partially by a void; and forming a gap fill dielectric after forming the gate, the gap fill dielectric being formed in the void such that the lower surface of the gate is separated from the global bit line by the gap fill dielectric; wherein after etching to form the first gate and the second gate, the gate dielectric extends continuously in a horizontal direction over a portion of the global bit line between the second S/D region of the first TFT select device and the second S/D region of the second TFT select device.