发明名称 L-shaped capacitor in thin film storage technology
摘要 The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.
申请公布号 US9397112(B1) 申请公布日期 2016.07.19
申请号 US201514645993 申请日期 2015.03.12
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Chuang Harry-Hak-Lay;Wu Wei Cheng;Chang Chien-Hung
分类号 H01L27/108;H01L27/115;H01L49/02;H01L29/51;H01L21/28 主分类号 H01L27/108
代理机构 Eschweiler & Associates, LLC 代理人 Eschweiler & Associates, LLC
主权项 1. An integrated capacitor, comprising: a first capacitor electrode disposed over a substrate; a charge trapping dielectric layer disposed onto the substrate at a position adjacent to the first capacitor electrode, wherein the charge trapping dielectric layer comprises an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction different than the first direction; a second capacitor electrode arranged onto the lateral component and separated from the first capacitor electrode by the vertical component, wherein an upper surface of the first capacitor electrode is substantially aligned with an upper surface of the second capacitor electrode; and wherein the first capacitor electrode and the second capacitor electrode are disposed over the substrate at positions that are laterally separated from a split-gate flash memory cell by a boundary region comprising one or more isolation structures arranged within the substrate and a dummy structure comprising a dummy select gate and a dummy control gate arranged laterally separated from the first capacitor electrode by a dielectric material overlying the substrate.
地址 Hsin-Chu TW