Memory buffering system that improves read/write performance and provides low latency for mobile systems

摘要

A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

主权项

1. A memory buffering system comprising:
a transfer bus; a unified memory controller (UMC) comprising a unified host buffer and a request queue; and a plurality of clients coupled together in a chain architecture, each of the plurality of clients comprising a respective memory element and a corresponding buffer, the respective memory element of each of the plurality of clients comprising a nonvolatile memory, the plurality of clients being configured to communicate with the unified host buffer in a series bus configuration, wherein the UMC is configured to allocate available buffer space of the corresponding buffer of each of the plurality of clients situated upstream from the respective memory element of a client being accessed from among the plurality of clients, wherein the UMC is further configured to selectively arbitrate bus ownership of the transfer bus for the plurality of clients according to a priority based scheme based on a number of requests pending from one or more of the plurality of clients, and wherein the respective memory element of each of the plurality of clients comprises a plurality of memory arrays and a plurality of state machines.