DATA RETENTION LATCH PROVISION WITHIN INTEGRATED CIRCUITS

摘要

There is provided an integrated circuit comprising: a plurality of processing stages, at least one of said processing stages having processing logic operable to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal; and a low power mode controller operable to control said integrated circuit to switch between an operational mode in which said integrated circuit performs said processing operations and a standby mode in which said integrated circuit retains signals values but does not perform said processing operations; wherein said at least one of said processing stages has: a non-delayed latch operable to capture a non-delayed value of said processing logic output signal at a non-delayed capture time; and a delayed latch operable during said operational mode to capture a delayed value of said processing logic output signal at a delayed capture time, said delayed capture time being later than said non- delayed capture time, said non-delayed value being passed as a processing stage input value to a following processing stage before said delayed capture time and a difference between said non-delayed value and said delayed value being indicative of said, processing operation not being complete at said non-delayed capture time; said delayed latch is operable during said standby mode to retain said delayed value whilst said non-delayed latch is powered down and loses said non-delayed value; and said delayed latch is formed to have a lower power consumption.