APPARATUS AND METHOD FOR ESTIMATING HIGH-INTEGRATION, HIGH-SPEED AND PIPELINED RECURSIVE LEAST SQUARES

摘要

Provided is an apparatus and method for estimating high-integration, high-speed and pipelined RLSs. Pipeline characteristics are given to an RLS algorithm to provide a high-speed HIP-RLS estimation apparatus. The HIP-RLS estimation apparatus has higher integration level than a conventional CORDIC-based RLS estimation apparatus. Thus, the use of the HIP-RLS estimation apparatus can reduce a chip size, thereby making it possible to fabricate more chips using the same wafer. Also, the HIP-RLS estimation apparatus is suitable for high-speed wireless communication because it has a high signal processing speed.