发明名称 EVALUATION DEVICE FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To evaluate plasma (process) included damage (PID) based on Vth shift to a device under test (DUT) in the substantial same area as an existent MISFET by applying a structure and a measurement technique to which well-known charge based capacitance measurement (CBCM) capable of performing minute capacitance measurement is applied.SOLUTION: When evaluating the PID including a pseudo inverter and a CBCM circuit including a gate capacitance DUT, a counter electrode is provided for an antenna that becomes a PID source and by supplying a clock signal of the same phase as a DUT gate, floating capacitance of the antenna is cancelled. The present technology may be applicable to CMOS.SELECTED DRAWING: Figure 6
申请公布号 JP2016092076(A) 申请公布日期 2016.05.23
申请号 JP20140221799 申请日期 2014.10.30
申请人 SONY CORP 发明人 MORI SHIGEKI
分类号 H01L21/822;H01L21/336;H01L21/66;H01L21/82;H01L21/8238;H01L27/04;H01L27/06;H01L27/092;H01L29/78 主分类号 H01L21/822
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