| 发明名称 |
PIPELINED HYBRID PACKET/CIRCUIT-SWITCHED NETWORK-ON-CHIP |
| 摘要 |
A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request. |
| 申请公布号 |
US2016182256(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201414574189 |
申请日期 |
2014.12.17 |
| 申请人 |
Intel Corporation |
发明人 |
Anders Mark A.;Kaul Himanshu;Chen Gregory K. |
| 分类号 |
H04L12/64;H04L12/50;H04L12/66;H04L12/24 |
主分类号 |
H04L12/64 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor to comprise:
a first router of a network-on-chip, the router to:
receive a packet-switched request from a second router of the network-on-chip, the packet-switched request to be generated at source logic, the packet-switched request identifying destination logic;receive circuit-switched data associated with the packet-switched request through a first circuit-switched channel;store the circuit-switched data associated with the packet-switched request; andsend the stored circuit-switched data towards the destination logic identified in the packet-switched request. |
| 地址 |
Santa Clara CA US |
