High-speed CMOS image sensor

摘要

A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.

主权项

id="REI-00001" date="20161129" 1. A complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising:
a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; a plurality of correlation double sampling (CDS) circuits coupled to corresponding columns of the pixel array; and a selection circuit comprising:
a plurality of input ends coupled to each CDS circuit of the plurality of CDS circuits respectively;a first output end;a second output end;a first switch coupling a 4n−3th CDS circuit to a first analog signal processor (ASP);a second switch coupling the 4n−3th CDS circuit to a second ASP;a third switch coupling a 4n−2th CDS circuit to the first ASP;a fourth switch coupling the 4n−2th CDS circuit to the second ASP;a fifth switch coupling a 4n−1th CDS circuit to the first ASP;a sixth switch coupling the 4n−1th CDS circuit to the second ASP;a seventh switch coupling a 4nth CDS circuit to the first ASP; anda eighth switch coupling the 4nth CDS circuit and to the second ASP;wherein n is a positive integer; wherein the first ASP is coupled to the first output end of the selection circuit for processing data of the plurality of first pixels and the plurality of second pixels; wherein the second ASP is coupled to the second output end of the selection circuit for processing data of the plurality of third pixels.