| 摘要 |
Structures and method for programmable memory address and decode circuits with ultra thin vertical body transistors are provided. The memory address and decode circuits includes a number of address lines and a number of output lines such that the address lines and the output lines form an array. A number of vertical pillars extend outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. A number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A floating gate opposes the ultra thin single crystalline vertical body region. Each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors for serving as a control gate.
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