STRUCTURE AND METHOD OF SUB-GATE AND ARCHITECTURES EMPLOYING BANDGAP ENGINEERED SONOS DEVICES

摘要

An integrated circuit device is provided to remove the coupling effect between floating gates by forming a shrinkable AND-type floating gate flash memory capable of maintaining effective hole tunneling erasing and overcoming a retention problem. A plurality of memory cells are formed on a semiconductor substrate, including a spacer dielectric layer between a gate and a sub-gate(130) disposed on a gate oxide layer wherein the gate is disposed on a stack of a blocking oxide layer(141), a charge storage layer(142) and a controlled tunnel dielectric layer. An N+ buried diffusion well is disposed in the semiconductor substrate, functioning as a first diffusion bitline and positioned in a portion under a gap between a first gate oxide layer and a stack of a first blocking layer, a charge storage layer and a controlled tunnel dielectric layer. The controlled tunnel dielectric layer can include a O2 layer(143), an N1 layer(144) and an O1 layer(145).