A level shifter circuit comprises a first transistor and a second transistor. The first transistor is connected to a power terminal and an output terminal and transfers a power voltage applied from the power terminal to the output terminal in response to an input signal, transferred from the input terminal to a first gate, and a signal transferred to a second gate. The second transistor is connected to the power terminal and transfers a grounding voltage to the output terminal in response to a gate signal transferred to a gate. Accordingly, the present invention can improve power efficiency in a depletion mode or an increase mode by forming a main transistor in the level shifter circuit as a double gate transistor.
申请公布号
KR20160103233(A)
申请公布日期
2016.09.01
申请号
KR20150025283
申请日期
2015.02.23
申请人
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人
PI, JAE EUN;BYUN, CHUN WON;KWON, OH SANG;PARK, EUN SUK;RYU, MIN KI;HWANG, CHI SUN