发明名称 Integrated circuitry for generating a clock signal in an implantable medical device
摘要 Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations.
申请公布号 US9397639(B2) 申请公布日期 2016.07.19
申请号 US201314077666 申请日期 2013.11.12
申请人 Boston Scientific Neuromodulation Corporation 发明人 Feldman Emanuel;Marnfeldt Goran N.;Parramon Jordi
分类号 G06F1/04;H03K3/03;A61N1/36;H03K3/011;H03K3/027;A61N1/05 主分类号 G06F1/04
代理机构 Lewis, Reese & Nesmith, PLLC 代理人 Lewis, Reese & Nesmith, PLLC
主权项 1. Circuitry for generating a clock signal, comprising: a high reference voltage and a low reference voltage; toggle circuitry configured to produce the clock signal, wherein the toggle circuitry is configured to set the clock signal to a first logic state when a feedback voltage is lower than the low reference voltage, and wherein the toggle circuitry is configured to set the clock signal to a second logic state when the feedback voltage is higher than the high reference voltage; and an RC circuit configured to produce the feedback voltage, wherein the feedback voltage charges when the clock signal is in one of the first or second logic states, and discharges when the clock signal is in the other of the first or second logic states, wherein the high and low reference voltages are simultaneously adjustable symmetrically around a midpoint of a first power supply voltage to adjust a frequency of the clock signal.
地址 Valencia CA US