发明名称 Full-bridge switching DC/DC converters and controllers thereof
摘要 A controller for a DC/DC converter controls a first, second, third, and fourth switches according to pulse signals generated alternately. The controller turns off the third switch on detection of a first edge of a first pulse signal, turns on the first switch after a delay from the detection of the first edge, turns off the fourth switch on detection of a second edge of the first pulse signal, turns on the second switch after a delay from the detection of the second edge, turns off the first switch on detection of a third edge of a second pulse signal, turns on the third switch after a delay from the detection of the third edge, turns off the second switch on detection of a fourth edge of the second pulse signal, and turns on the fourth switch after a delay from the detection of the fourth edge.
申请公布号 US9397579(B2) 申请公布日期 2016.07.19
申请号 US201414250050 申请日期 2014.04.10
申请人 O2Micro Inc 发明人 Popovici Catalin;Gherghescu Alin;Lipcsei Laszlo
分类号 H02M3/335;H02M1/00 主分类号 H02M3/335
代理机构 代理人
主权项 1. A controller for a DC/DC converter, said controller comprising: a signal generator operable for transferring pulses of a PWM (pulse width modulation) signal to a first channel and a second channel alternately thereby generating a first pulse signal at said first channel and a second pulse signal at said second channel alternately, and operable for controlling said PWM signal to regulate an output of said DC/DC converter; and control circuitry, coupled to said signal generator, operable for controlling a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch according to said first and second pulse signals, wherein said controlling comprises: turning off said third switch in response to detecting a first edge of said first pulse signal, and turning on said first switch after a predetermined delay from said detecting of said first edge,turning off said fourth switch in response to detecting a second edge of said first pulse signal, and turning on said second switch after a predetermined delay from said detecting of said second edge,turning off said first switch in response to detecting a third edge of said second pulse signal and turning on said third switch after a predetermined delay from said detecting of said third edge, andturning off said second switch in response to detecting a fourth edge of said second pulse signal and turning on said fourth switch after a predetermined delay from detecting of said fourth edge, wherein said control circuitry is operable for generating a plurality of driving signals according to said first and second pulse signals, and each driving signal of said driving signals has a turn-on status to turn on a corresponding switch in said switches and a turn-off status to turn off said corresponding switch, and wherein said control circuitry further comprises: a plurality of delay units, comprising a first delay unit, a second delay unit, a third delay unit, and a fourth delay unit, operable for generating said driving signals according to a plurality of logic outputs, each logic output of said logic outputs having a first level and a second level, wherein said first delay unit is operable for setting a first driving signal of said driving signals to said turn-on status after a predetermined delay from detecting that a first logic output of said logic outputs is at said first level, and setting said first driving signal to said turn-off status in response to detecting that said first logic output is at said second level, wherein said second delay unit is operable for setting a second driving signal of said driving signals to said turn-on status after a predetermined delay from detecting that a second logic output of said logic outputs is at said first level, and setting said second driving signal to said turn-off status in response to detecting that said second logic output is at said second level, wherein said third delay unit is operable for setting a third driving signal of said driving signals to said turn-on status after a predetermined delay from detecting that a third logic output of said logic outputs is at said first level, and setting said third driving signal to said turn-off status in response to detecting that said third logic output is at said second level, and wherein said fourth delay unit is operable for setting a fourth driving signal of said driving signals to said turn-on status after a predetermined delay from detecting that a fourth logic output of said logic outputs is at said first level, and setting said fourth driving signal to said turn-off status in response to detecting that said fourth logic output is at said second level.
地址 Santa Clara CA US