发明名称 POWER MANAGEMENT SYNCHRONIZATION MESSAGING SYSTEM
摘要 A multi-die package for a microprocessor provides a power management synchronization system. The package has a plurality of dies. Each die has a plurality of cores, including a single master core. A plurality of sideband non-system-bus inter-die communication wires communicatively couple the dies to each other for a purpose of synchronizing power management. The master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores. The master core of each die is also configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires. The cores use this system of inter-die communication wires to synchronize management of resources that affect both the performance and power consumption of the cores.
申请公布号 US2016209897(A1) 申请公布日期 2016.07.21
申请号 US201514980209 申请日期 2015.12.28
申请人 VIA TECHNOLOGIES, INC. 发明人 HENRY G. GLENN;GASKINS DARIUS D.
分类号 G06F1/26 主分类号 G06F1/26
代理机构 代理人
主权项 1. A multi-die package for a microprocessor comprising: a plurality of dies; each die having a plurality of cores, including a single master core; and a plurality of sideband non-system-bus inter-die communication wires communicatively coupling the dies to each other for a purpose of synchronizing power management; wherein the master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores; wherein the master core of each die is configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires.
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