发明名称 PCIE lane aggregation over a high speed link
摘要 A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
申请公布号 US9430437(B1) 申请公布日期 2016.08.30
申请号 US201313963329 申请日期 2013.08.09
申请人 INPHI CORPORATION 发明人 Krishnan Sreenivas;Saxena Nirmal Raj
分类号 G06F13/40;H04L12/64;H04L12/66;H04J14/02 主分类号 G06F13/40
代理机构 Ogawa P.C. 代理人 Ogawa Richard T.;Ogawa P.C.
主权项 1. A computer network system, the system comprising: an I/O appliance comprising: a network processor;a plurality of optical ports numbered from 1 to N;a downstream aggregating silicon photonics device provided on each of the plurality of optical ports;a SSD (Solid-State Drive) interface coupled to each of the optical ports;a NIC (Network Interface Controller) interface coupled to each of the optical ports;a top of rack switch coupled to each of the NIC interfaces;a plurality of spine switches coupled to the top of rack switches; and a plurality of server devices coupled to the I/O appliance, each of the server devices comprising: a memory storage device;a CPU (Central Processing Unit) device coupled to the memory storage device using a DDR interface;a PCIe (Peripheral Component Interconnect Express) interface configured with the CPU device; and an upstream aggregating silicon photonics device coupled to the plurality of server devices and aggregating each of the PCIe interfaces.
地址 Santa Clara CA US