发明名称 |
Non-planar quantum well device having interfacial layer and method of forming same |
摘要 |
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. |
申请公布号 |
US9502568(B2) |
申请公布日期 |
2016.11.22 |
申请号 |
US201514804019 |
申请日期 |
2015.07.20 |
申请人 |
Intel Corporation |
发明人 |
Rachmady Willy;Pillarisetty Ravi;Le Van H.;Chau Robert S. |
分类号 |
H01L29/06;H01L31/00;H01L29/78;B82Y10/00;H01L29/66;H01L29/775;H01L29/267;H01L29/10;H01L29/15;H01L29/165;H01L29/51 |
主分类号 |
H01L29/06 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A system comprising:
a memory; at least one of a processor and a controller coupled to the memory; and a non-planar quantum well device comprising:
a quantum well structure comprising a quantum well layer and at least one of a IV and III-V material barrier layer, the quantum well layer including a channel region;a fin structure (a) in the quantum well structure, and (b) including the quantum well layer;a high-k layer over the fin structure; anda gate metal over the high-k layer. |
地址 |
Santa Clara CA US |