Wafer level packaging of electronic device

摘要

Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.

主权项

1. A wafer level packaging of semiconductor devices comprising:
a semiconductor device with a top face and a bottom face and one or more metal pads with each metal pad located on either the top face or the bottom face and; a top cover wafer affixed to the top face of the semiconductor device and; a bottom cover wafer affixed to the bottom face of the semiconductor device; wherein the top cover wafer and the bottom cover wafers have one or more vias extending from an external face of the respective cover wafer to an internal face of said cover wafer, wherein each of the one or more vias is associated with one of the one or more metal pads; and wherein an electroplated metal layer extends from the external face of each of the respective cover wafers through the via to the metal pad associated with the via.