Congestion aware layer promotion

摘要

Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

主权项

1. A system to manage layer promotion in a routing phase of integrated circuit design, the system comprising:
a memory device configured to store instructions; and a processor configured to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects, wherein the processor scores the set of candidate interconnects based on determining, for each candidate interconnect of the set of candidate interconnects, an amount of time by which the candidate interconnect exceeds a timing requirement and a degree to which a length of a path including the candidate interconnect exceeds a minimum possible length of the path, and the processor scores the set of candidate interconnects based on calculating, for the respective candidate interconnect, a score given by:
score =scalingt*t_metric+scalingp*p_metric, where scalingt and scalingp are scaling factors, t_metric relates to the amount of time by which the candidate interconnect exceeds the timing requirement, and p_metric relates to the degree to which the length of the path including the candidate interconnect exceeds the minimum possible length of the path.