| 摘要 |
A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level. The node voltage controller acts as voltage divider to maintain a voltage difference across the gate-to-drain of the pull-up circuit within the operating tolerance of the pull-up circuit (Vtp+2*Vtn). |
