| 摘要 |
In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array.
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