发明名称 Splitable and scalable normalizer for vector data
摘要 A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.
申请公布号 US9361267(B2) 申请公布日期 2016.06.07
申请号 US201314016607 申请日期 2013.09.03
申请人 International Business Machines Corporation 发明人 Boersma Maarten J.;Kaltenbach Markus;Layer Christophe J.;Mueller Silvia M.
分类号 G06F15/78;G06F15/80 主分类号 G06F15/78
代理机构 代理人 Carpenter Maeve M.;Patel Jinesh P.
主权项 1. A hardware circuit for supporting vector operations in a scalar data path, the hardware circuit comprising: a hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration, wherein the vector mode configuration supports two operands of some bit size, and the scalar mode configuration supports a single operand of some bit size greater than either vector operand bit size; and the hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration, wherein the hardware circuit component is further configured to determine a location for splitting the scalar mode configuration into a left half and a right half of the vector mode configuration through a formulaic relationship between an output string width, a number of fine shift multiplexers, a number of inputs per fine shift multiplexer, and a number of coarse shift multiplexers of a normalizer circuit, wherein the left half of the vector mode configuration receives a left control signal to independently control select signals left of the split, and the right half of the vector mode configuration receives a right control signal to independently control select signals right of the split.
地址 Armonk NY US