Capping layer for improved deposition selectivity

摘要

The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.

主权项

1. A back-end-of-the-line (BEOL) layer of an integrated chip, comprising:
a low-k dielectric layer disposed over a semiconductor substrate; one or more metal layer structures disposed within the low-k dielectric layer and comprising a copper metal; a first capping layer located over the low-k dielectric layer at positions between the one or more metal layer structures, wherein the first capping layer is located along a planar interface having the one or more metal layers structures interspersed between the first capping layer; and a second capping layer located over the one or more metal layer structures, wherein the second capping layer has a greater thickness in areas overlying the copper metal than in areas not overlying the copper metal, causing the second capping layer to have vertical sidewalls that are laterally aligned with vertical sidewalls of the copper metal.