Method for improved accuracy of a substrate parasitic-resistance extraction in a circuit simulation

摘要

By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.

主权项

1. A circuit simulation method comprising:
dividing a well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate into two or more meshes each including two or more resistor segments; and analyzing a substrate noise of the substrate, wherein parallel components of resistors coupling said Pwell with said substrate are deleted in accordance with a state of said Deep Nwell diffusing into said Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value, wherein said process for expressing the rise in the resistance value is a resistor segment deleting process in which, after said mesh division, resistor segments in a depth direction of said semiconductor substrate are deleted in a mesh corresponding to said Pwell region eroded by the diffusion of said Deep Nwell.