NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To increase write operation speed by enabling simultaneous verification of many bits when verifying a program.

SOLUTION: The source line SL of a memory cell Trm formed in the N well of a memory cell array 11 is connected to a column source line CSL being a source line in a block and a block source line BSL in common, and the line SL is connected to a source line MSL outside the block via a block source select gate BSSG. This source line MSL outside the block is a metal layer of the upper most layer and wired so as to extend in a Y axis direction (bit line direction). A cell current made to flow from the bit line by output of a column latch via a memory cell in which write is completed is bypassed by this source line MSL outside the block.

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