| 摘要 |
A dual-bias erase process for a non-volatile memory device is described. The dual-bias erase process applies a positive bias to the source and drain regions of the memory device, while simultaneously applying a negative bias to the gate region of the memory device. Since a negative bias is applied to the gate, and since no bias is applied from the source to the drain, the memory device is not "turned on" and no electric current will flow through the channel under the gate. The positive biases on the source and drain regions, however, generate minority carriers that are attracted to the gate region by its negative bias. These minority carriers are injected into the nitride by the negative gate bias, thereby erasing any previous programming of the memory device.
|
