Insulating gate AlGaN/GaN HEMT

摘要

AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

主权项

1. A high electron mobility transistor (HEMT), comprising:
a high resistivity semiconductor layer comprising a Group-III nitride semiconductor material; a barrier semiconductor layer comprising a Group-III nitride semiconductor material on said high resistivity semiconductor layer, said barrier semiconductor layer comprising a wider bandgap than said high resistivity semiconductor layer; a two-dimensional electron gas (2-DEG) between said high resistivity semiconductor layer and said barrier layer; a Group-III nitride insulating spacer layer on said barrier layer; an insulating layer, said insulating layer on said insulating spacer layer such that said insulating spacer layer is between said insulating layer and said barrier semiconductor layer; a gate contact on said insulating layer, wherein said gate contact is insulated from said barrier semiconductor layer by said insulating spacer layer and said insulating layer; respective source and drain contacts contacting said barrier layer and said high resistivity semiconductor layer, wherein said insulating spacer layer is between said source and said drain contacts; and a dielectric layer on said insulating layer comprising a first portion between and in contact with said source contact and said gate contact and a second portion between and in contact with said gate contact and said drain contact, wherein upper portions of side surfaces of said gate contact are uncovered by said dielectric layer.