发明名称 Process for 3D NAND memory with socketed floating gate cells
摘要 A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
申请公布号 US9419006(B2) 申请公布日期 2016.08.16
申请号 US201414494873 申请日期 2014.09.24
申请人 SanDisk Technologies LLC 发明人 Cernea Raul Adrian
分类号 H01L21/336;H01L27/115 主分类号 H01L21/336
代理机构 Davis Wright Tremaine LLP 代理人 Davis Wright Tremaine LLP
主权项 1. A method of forming a 3D NAND memory, comprising: forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of vertically aligned NAND strings, and wherein the layers includes memory cell layers for forming memory cells of the NAND strings and for forming word lines with socket components; opening trenches in the multi-layer slab to expose the memory cell layers; forming grottoes at where memory cells are to be formed in the memory cell layers exposed by the trenches, each grotto having walls; forming in each grotto a socket component of a word hue by lining the walls with deposition of a word line material; depositing a layer of insulating material on the word line material lining the walls while leaving a remaining space in each grotto; filling the remaining space of each grotto with a floating gate material to form a floating gate embedded in each grotto; forming other structures of the NAND strings and a plurality of bit lines through the trenches; and partitioning the multi-layer slab by an isolation material into individual memory cells accessible by respective word lines and bit lines.
地址 Plano TX US