Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

摘要

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a first core to perform instructions; an accelerator to perform at least one operation on data to be received from the first core, wherein the accelerator is a heterogeneous resource with respect to the first core and comprising a sequencer having next instruction pointer logic to determine a next instruction to be executed by the accelerator, the accelerator comprising a graphics processor having a plurality of processing engines, at least some of the plurality of processing engines to be disabled for execution of a graphics function by configuration of a system including a graphics component to perform the graphics function according to a disable indicator programmed by a basic input/output system (BIOS), the at least some of the plurality of processing engines to execute a task unrelated to the graphics function responsive to a command from the first core; and an interface logic coupled to the accelerator to enable inter-sequencer communication between the first core and the accelerator, the interface logic to receive the inter-sequencer communication and translate the inter-sequencer communication to a native instruction sequence of the accelerator, wherein the accelerator is to perform a first operation responsive to the native instruction sequence in parallel with performance of a second operation in the first core, the second operation independent from the first operation.