Intelligent caching for an operand cache

摘要

Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may store a subset of operands, and may use less power and have quicker access times than the register file. In some embodiments, intelligent operand prefetching may speed execution by reducing memory bank conflicts (e.g., conflicts within a register file containing multiple memory banks). An unused operand slot for another instruction (e.g., an instruction that does not require a maximum number of source operands allowed by an instruction set architecture) may be used to prefetch an operand for another instruction in one embodiment. Prefetched operands may be stored in an operand cache, and prefetching may occur based on software-provided information.

主权项

1. An apparatus, comprising:
an execution unit configured to execute instructions having up to N possible source operands, wherein N is greater than 1; a register file configured to store a plurality of operands for instructions to be executed by the execution unit; an operand cache configured to store a subset of the plurality of operands stored in the register file; and fetch circuitry configured to retrieve operands specified by instructions to be executed by the execution unit, wherein the fetch circuitry, in response to a particular instruction using fewer than N source operands, is configured to prefetch one or more operands from the register file and store the one or more prefetched operands in the operand cache, and wherein the one or more operands are for an instruction other than the particular instruction.