Method and apparatus for asynchronous processor with fast and slow mode

摘要

A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

主权项

1. A clock-less asynchronous processing system, comprising:
a processing pipeline having a plurality of successive processing stages, and a first processing stage comprising,
asynchronous logic circuitry configured to process input data and output processed data,a data storage element coupled to the asynchronous logic circuitry and configured to receive and store the processed output data in response to an active complete signal, and a self-clocked generator configured to generate and output the active complete signal to the data storage element after a first period of time after receipt of a trigger signal when in a first mode and after a second period of time after receipt of the trigger signal when in a second mode, wherein the first mode is an initialization mode and the second mode is a normal mode.