| 摘要 |
PROBLEM TO BE SOLVED: To provide a TEG pattern, and a testing method of a semiconductor element using the pattern capable of confirming a leakage current level generated by erroneously aligned landing to an active region of M1C through silicon substrate data in a viewpoint of an active extension design rule to the M1C in a manufacturing method of a semiconductor device of 90 nm class or below. SOLUTION: The TEG pattern includes a plurality of element isolation film patterns 123 with a predetermined space between; an active region pattern 125 formed between these element isolation film patterns 123; and a metal 1 contact pattern 127 formed in the active region pattern 125. COPYRIGHT: (C)2008,JPO&INPIT
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