| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce power consumption and EMI and to secure wiring resources to facilitate wiring when a master-slave type flip-flop circuit is actualized using a gate array. <P>SOLUTION: A master latch 1 comprises an inverter 11, clocked inverters 12 and 13 with enable, and a latch circuit 14. A slave latch 1 includes a transmission gate 21 and a latch circuit 22. Respective elements configuring the latches 1 and 2 are configured with basic cells configuring a gate array. A basic cell of the gate array consists of triplely arrayed N type MOS transistors and triplely arrayed P type MOS transistors corresponding thereto. The triplely arrayed N type MOS transistors consist of double arrayed normally sized main transistors and one auxiliary transistor sized smaller than that of a normal size. The triplely arrayed P type MOS transistors are also similarly constituted. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
