Semiconductor storage device having an SRAM memory cell and control and precharge circuits

摘要

A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

主权项

1. A semiconductor storage device comprising:
an SRAM memory cell that includes a drive transistor, a transfer transistor and a load transistor; an I/O circuit that is connected to first and second bit lines which are connected to the memory cell; and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes: a write driver that writes data to the first and second bit lines, a sense amplifier that reads data from the first and second bit lines, first and second precharge circuits that precharge the first and second bit lines, and a control circuit that controls the first and second precharge circuits according to a signal from the operating mode control circuit, wherein the control circuit turns off the first and second precharge circuits in the resume standby mode, turns on the second precharge circuit when returning from the resume standby mode to the normal operation mode and turns on the first precharge circuit in the normal operation mode.