发明名称 |
Method and apparatus for handling imprecise exceptions |
摘要 |
<p>A method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one aspect of the invention, a method is provided in which a macro-instruction is decoded into a first and second micro-instructions. The macro-instruction designates an operation on a pieced of data, and execution of the first and second micro-instructions separately cause the operation to be performed on different parts of the piece of data. The method also requires that the first micro-instruction is executed irrespective of the second micro-instructions (e.g., at a different time), and that it is detected that said second micro-instruction will not cause any non-recoverable exceptions. The results of the first micro-instruction are then used to update the architectural state in an earlier clock cycle than said second micro-instruction. <IMAGE></p> |
申请公布号 |
EP0947917(A2) |
申请公布日期 |
1999.10.06 |
申请号 |
EP19990302337 |
申请日期 |
1999.03.25 |
申请人 |
INTEL CORPORATION |
发明人 |
ABDALLAH, MOHAMMAD;PENTKOVSKI, VLADIMIR |
分类号 |
G06F9/30;G06F9/302;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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