Dual-mode counter-divider circuit for very high frequency operation

摘要

The circuit (1) has two NAND gates (15, 16) arranged in negative feedback between two dynamic D-type flip flops (12, 13) which are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency is matched with an input clock signal frequency divided by a factor equal to 2 or 3 as a function of a division mode selection signal (divb) applied to an input of one of the NAND gates. An output of one flip flop is connected to an input of the other flip flop, where one of the flip flops is formed of three active branches to provide only one inverted output signal.