| 摘要 |
PURPOSE: A pulse width control circuit for a column address is provided to prevent a second read fail by controlling the pulse width of a column address signal in read operation. CONSTITUTION: In a pulse width control circuit for a column address, a decoding driver decodes a column address signal. An enable unit enables a decoding driver. A variable control unit variable-controls the driving force of the decoding driver. The variable control unit comprises an adjust unit and the variable control unit. An adjusting unit generates a control signal according to a write operation mode. The adjusting unit is comprised of a delay unit(10) and an inverter unit(13). The delay unit delays a WTS signal. The inverter unit is comprised of three inverters. A NAND gate(25) generates the enable signal. |
