Nonvolatile semiconductor memory device with block decoder

摘要

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

主权项

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including a first block and a second block, the first block including a first memory string, the first memory string including a first selection transistor and a plurality of first memory cells connected in series, the second block including a second memory string, the second memory string including a second selection transistor and a plurality of second memory cells connected in series; a plurality of first transfer transistors connected to gates of the plurality of first memory cells and a gate of the first selection transistor; a plurality of second transfer transistors connected to gates of the plurality of second memory cells and a gate of the second selection transistor; a third transfer transistor having a first end connected to an end of one of the first transfer transistors and the gate of the first selection transistor; a fourth transfer transistor having a first end connected to an end of one of the second transfer transistors and the gate of the second selection transistor; and a first block decoder configured to output a first selection signal to gates of the first and second transfer transistors and a first non-selection signal to gates of the third and fourth transfer transistors, a first output of the first block decoder being connected to the gates of the first and second transfer transistors and a second output of the first block decoder being connected to the gates of the third and fourth transfer transistors.