Vertical memory device and method for making thereof

摘要

Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.

主权项

1. A method comprising:
providing a semiconductor substrate; providing (i) a first top layer on the semiconductor substrate and (ii) a second top layer on the first top layer, thereby forming a semiconducting substrate comprising the semiconductor substrate, the first top layer, and the second top layer, wherein the first top layer comprises a first type of dopants and the second top layer comprises a second type of dopants different from the first type of dopants; providing a stack of layers on the semiconducting substrate, wherein the stack of layers comprises at least a first dielectric layer, a conductive layer formed on the first dielectric layer, and a second dielectric layer formed on the conductive layer; providing a hole in the stack of layers, thereby exposing a portion of the semiconducting substrate; providing a gate dielectric at least at opposing sidewall surfaces that define the hole; providing a substantially undoped semiconducting material in the hole, thereby forming a middle region of a vertical memory device in the hole; providing a doped semiconducting material on the stack and on the substantially undoped semiconducting material in the hole, wherein the doped semiconducting material comprises the first type of dopants; using a first anneal to form a bottom part of the vertical memory device in the hole, wherein the bottom part comprises (i) a first bottom region adjacent to the second top layer and comprising the first type of dopants and (ii) a second bottom region adjacent to the first bottom region and the middle region and comprising the second type of dopants; and using a second anneal to form a top region of the vertical memory device in the hole, wherein the top region is adjacent to the middle region and comprises the first type of dopants.