发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type provided between each of the second semiconductor regions and the second electrode, an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions. |
申请公布号 |
US9425307(B2) |
申请公布日期 |
2016.08.23 |
申请号 |
US201514636636 |
申请日期 |
2015.03.03 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Kono Hiroshi |
分类号 |
H01L29/76;H01L29/78;H01L29/94;H01L29/423;H01L29/36;H01L29/66;H01L29/16 |
主分类号 |
H01L29/76 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A semiconductor device comprising:
a first electrode; a second electrode; a first semiconductor region of a first conductivity type between the first electrode and the second electrode; a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode; a third semiconductor region of the first conductivity type provided between the second semiconductor regions and the second electrode; an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions, wherein the corners of the third electrode are inset into end portions of the second semiconductor region, such that a portion of the second semiconductor region extends between the inset portion of the third electrode and the first semiconductor region. |
地址 |
Tokyo JP |